Storage controller having soft decoder included therein, related storage control method thereof and system using the same

ABSTRACT

An exemplary storage controller for controlling data access of a storage device includes a control circuit and a soft decoder. The control circuit is utilized for reading data from the storage device to obtain readout data. The soft decoder is coupled to the control circuit, and utilized for performing a soft decoding operation upon the readout data to generate decoded data. The soft decoder may be a low density parity check (LDPC) decoder, a block turbo code (BTC) decoder, or a convolutional turbo code (CTC) decoder. The storage device may be a flash memory device.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No. 61/163,951, filed on Mar. 27, 2009 and incorporated herein by reference.

BACKGROUND

The disclosed embodiments of the present invention relate to recording data into and/or reading data from a storage device, and more particularly, to a storage controller having a soft decoder included therein, a related storage control method thereof, and a system using the same.

Error detection and correction techniques are employed to effectively correct errors caused by various factors to obtain error-free data. Taking a flash memory for example, continuous improvements in price/performance for the flash memory have enabled the flash memory to become the long term storage of choice for many applications; however, during the fabrication, the flash memory may contain defects (e.g., defective memory cells), and more defects may appear during the device lifetime, thereby limiting its usage. To manage these defects and to achieve efficient and reliable operation, the memory system typically uses error detection and correction techniques to control errors and to ensure reliable data reproduction.

In a typical NAND flash device, only the hard coding scheme, such as the Reed-Solomon (RS) coding or Bose-Chaudhuri-Hocquenghem (BCH) coding, is employed to detect and correct data errors. However, in a case where the bit error rate (BER) is quite poor, there is no significant improvement on the coding gain. In other words, when the original BER is quite poor, the hard decoder (e.g., an RS decoder or a BCH decoder) fails to effectively improve the BER.

Therefore, how to improve the error correcting capability of a storage device (e.g., a NAND flash device) becomes an issue to be solved by a designer in the pertinent field.

SUMMARY

In accordance with exemplary embodiments of the present invention, a storage controller having a soft decoder included therein, a related storage control method thereof, and a system using the same are disclosed.

According to a first aspect of the present invention, an exemplary storage controller for controlling data access of a storage device is disclosed. The exemplary storage controller includes a control circuit and a soft decoder. The control circuit is configured for reading data from the storage device to obtain readout data. The soft decoder is coupled to the control circuit, and implemented for performing a soft decoding operation upon the readout data to generate decoded data.

According to a second aspect of the present invention, an exemplary storage control method for controlling data access of a storage device is disclosed. The exemplary storage control method includes: reading data from the storage device to obtain readout data; and performing a soft decoding operation upon the readout data to generate decoded data.

According to a third aspect of the present invention, an exemplary system having a storage device and a storage controller is disclosed. The storage controller is coupled to the storage device, and implemented for controlling data access of the storage device. A data signal transmitted from the storage device to the storage controller carries soft information derived from the storage device.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a first exemplary embodiment of a storage controller according to the present invention.

FIG. 2 is a diagram illustrating the relationship between the coding gain and the bit error rate when a soft coding scheme is employed.

FIG. 3 is a block diagram of a second exemplary embodiment of a storage controller according to the present invention.

FIG. 4 is a block diagram illustrating an exemplary system having a storage controller included therein.

FIG. 5 is a diagram showing an exemplary control and data flow of the system shown in FIG. 4.

DETAILED DESCRIPTION

Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Generally speaking, the error detection and correction requires proper data encoding and data decoding. Provided that input data are encoded using a specific error correction code (ECC) scheme, decoding the encoded input data by hard decoding and decoding the same encoded input data by soft decoding may have different computational complexity, respectively. Taking a BCH code with a long codeword length for example, the computational complexity of decoding the BCH code using the soft decoding manner is too high to be acceptable. Therefore, compared with decoding the BCH code using the soft decoding means, decoding the BCH code using the hard decoding means would be easier and may be preferably employed. With regard to other coding scheme, such as a low density parity check (LDPC) code, a block turbo code (BTC), or a convolutional turbo code (CTC), the soft decoding complexity thereof is low and acceptable. Thus, employing the soft decoding means to decode the LDPC/BTC/CTC code may be preferably employed. It should be noted that data to be decoded by the hard decoding are data that include 1's and 0's generated by binary decision (quantization); however, data to be decoded by the soft decoding may be data which are not processed by binary decision (quantization).

To clarify the terminology in the following specification paragraphs and claims, certain terms, including “soft encoder”, “hard encoder”, “soft encoding operation” and “hard encoding operation,” are first defined here. If the computational complexity of decoding encoded data, generated from a specific encoder employing a specific coding scheme, by the soft decoding is within a predetermined acceptable range, the specific encoder is termed “soft encoder” and the employed specific coding scheme is termed “soft encoding operation”. However, if the computational complexity of decoding the encoded data (generated from the specific encoder employing the specific coding scheme) by the soft decoding is beyond the predetermined acceptable range, the specific encoder is termed “hard encoder” and the employed specific coding scheme is termed “hard encoding operation”. By way of example, not limitation, the soft encoder implemented in the exemplary embodiments of the present invention is to produce encoded data applicable to a soft decoding operation which requests acceptable computational complexity, and the hard encoder implemented in the exemplary embodiments of the present invention is to produce encoded data inapplicable to a soft decoding operation which requests acceptable computational complexity.

The conception of the present invention is to have a soft encoder involved in processing data to be stored into a storage device (e.g., a NAND flash memory), and a soft decoder involved in processing data read from the storage device. Therefore, in a situation where the BER is poor, there is a significant improvement on the coding gain. In other words, when the original BER is poor, the soft decoder is capable of effectively improving the BER.

FIG. 1 is a block diagram of a first exemplary embodiment of a storage controller according to the present invention. The exemplary storage controller 100 includes, but is not limited to, a soft encoder 110, a control circuit 120, and a soft decoder 130. It should be noted that only the elements pertinent to the present invention are shown in FIG. 1 for simplicity and clarity. In an actual implementation, the storage controller 100 may include other elements, such as a data buffer. The storage controller 100 is used for controlling data access of a storage device 102, and communicates with a host 106 via a host interface 104. By way of example, not limitation, the storage device 102 is a flash memory device, such as a NAND flash application. When the storage controller 100 receives a host output D1 from the host 106 via the host interface 104, the soft encoder 110 performs a soft encoding operation upon input data D1″ to generate encoded data D1′, where the input data D1″ are generated from the host input D1. For example, the input data D1″ are generated from the host input D1 without any change made to the host input D1. In other words, the input data D1″ and the host input D1 are exactly the same. In addition, the soft encoder 110 may be an LDPC encoder, a BTC encoder, or a CTC encoder. However, this is for illustrative purposes only, and is not meant to be taken as a limitation to the scope of the present invention. That is, any coding scheme can be employed by the soft encoder 110 in the exemplary storage controller 100, wherein the coding scheme is capable of producing encoded data applicable to a soft decoding operation with acceptable computational complexity.

The control circuit 120 is coupled to the soft encoder 110 and the storage device 102, and is configured to record data into the storage device 102 according to the encoded data D1′ generated from the soft encoder 110. In one implementation, the control circuit 120 may directly store the encoded data D1′ into the storage device 102 to accomplish the write operation. In another implementation, the control circuit 120 further processes the encoded data D1′, and then stores a processing result of the encoded data D1′ into the storage device 102 to accomplish the write operation. For example, the control circuit 120 performs a bit interleaving operation upon the encoded data D1′, and then stores a bit-interleaved result of the encoded data D1′ into the storage device 102.

With regard to the read operation, the control circuit 120 reads data from the storage device 102 to obtain readout data E1. For example, in a case where the control circuit 120 directly stores the encoded data D1′ generated from the soft encoder 110 into the storage device 102 to accomplish the write operation, the data read from the storage device 102 are representative of the encoded data D1′. Therefore, the control circuit 120 directly obtains the readout data E1 from the data read from the storage device 102. However, in another case where the control circuit 120 applies specific signal processing upon the encoded data D1′ prior to storing the encoded data D1′ into the storage device 102 (e.g., the control circuit 120 performs a bit interleaving operation upon the encoded data D1′, and then stores a bit-interleaved result of the encoded data D1′ into the storage device 102), the data read from the storage device 102 are representative of a specific signal processing result of the encoded data D1′ rather than the encoded data D1′. Therefore, the control circuit 120 applies an inverse signal processing operation (e.g., a bit deinterleaving operation) upon the data read from the storage device 102 to generate a corresponding signal processing result (e.g., a bit-deinterleaved result), and then obtains the readout data E1 from the corresponding signal processing result.

The soft decoder 130 is used for performing a soft decoding operation upon the readout data E1 to generate decoded data E1′. For example, when the soft encoder 110 is an LDPC encoder, the readout data E1 include LDPC codewords, and the soft decoder 130 is an LDPC decoder which decodes the LDPC codewords of the readout data E1 to generate the decoded data E1′; when the soft encoder 110 is a BTC encoder, the readout data E1 include BTC codewords, and the soft decoder 130 is a BTC decoder which decodes the BTC codewords of the readout data E1 to generate the decoded data E1′; and when the soft encoder 110 is a CTC encoder, the readout data E1 include CTC codewords, and the soft decoder 130 is a CTC decoder which decodes the CTC codewords of the readout data E1 to generate the decoded data E1′. In the end, the control circuit 120 transmits a host input E1″ to the host 106 via the host interface 104 to accomplish the read operation, where the host input E1″ is generated from the decoded data E1′. For example, the host input E1″ is generated from the decoded data E1′ without any change made to the decoded data E1′. In other words, the host input E1″ and the decoded data E1′ are exactly the same.

It should be noted that when the storage device 102 is read, the data signal transmitted from the storage device 102 to the control circuit 120 carries soft information read from the storage device 102, where the data signal may be an analog signal (e.g., an analog voltage signal) or a multi-level (multi-bit) signal. In a case where the data signal is an analog voltage signal which transfers an analog voltage derived from reading a data bit stored in each memory cell of the storage device 102, the control circuit 120 has an analog-to-digital conversion capability to convert the analog voltage signal in an analog domain into digital soft bits in a digital domain, and then obtains the readout data E1 according to the digital soft information. As the present invention does not focus on the generation and transmission of the soft information, further description is omitted here for the sake of brevity.

As mentioned above, when the original BER is poor, there is no significant improvement on the coding gain by solely using the hard encoder/decoder. For example, when the original BER is 10⁻², the hard decoder fails to effectively improve the BER from 10⁻² to 10⁻³ due to the inherent characteristic of the hard coding scheme. However, as shown in FIG. 2 which illustrates the relationship between the coding gain and the BER when a soft coding scheme is employed, the soft decoder (e.g., an LDPC decoder) is capable of effectively improving the coding gain when the original BER is poor. The ‘SNR’ in FIG. 2 means signal-to-noise ratio.

In view of above, an exemplary storage control method employed by the storage controller 100 shown in FIG. 1 for controlling data write of a storage device (e.g., a flash memory device) includes following steps: performing a soft encoding operation upon input data to generate encoded data, and recording data into the storage device according to the encoded data, where the computational complexity of decoding the encoded data via soft decoding is within a predetermined acceptable range; additionally, the exemplary storage control method employed by the storage controller 100 shown in FIG. 1 for controlling data read of the storage device includes following steps: reading data from the storage device to obtain readout data, and performing a soft decoding operation upon the readout data to generate decoded data. As a person skilled in the art can readily understand details of the exemplary storage control method after reading above paragraphs directed to the storage controller 100, further description is omitted here for brevity.

In above embodiment shown in FIG. 1, a single soft encoder/decoder architecture is employed. However, this is for illustrative purposes only. In an alternative design, a concatenated coding scheme may be employed to achieve a better error correcting capability. As shown in FIG. 2, when the BER is not so bad (e.g., BER<10⁻⁶), there is no significant improvement on the coding gain by solely using the soft encoder/decoder in the storage controller. However, when the BER is not so bad (e.g., BER<10⁻⁶), the use of the hard encoder/decoder is capable of offering a significant improvement on the coding gain. For example, the hard decoder in a read operation can effectively improve the original BER from 10⁻⁶ to 10⁻¹⁴ or even smaller (not shown). Based on the above observation, an improved storage controller architecture is proposed.

Please refer to FIG. 3, which is a block diagram of a second exemplary embodiment of a storage controller according to the present invention. The exemplary storage controller 300 includes, but is not limited to, a soft encoder 310, a hard encoder 320, a control circuit 330, a soft decoder 340, and a hard decoder 350. It should be noted that only the elements pertinent to the present invention are shown in FIG. 3 for simplicity and clarity. In an actual implementation, the storage controller 300 may include other elements, such as a data buffer.

The storage controller 300 is used for controlling data access of a storage device 302, and communicates with a host 306 via a host interface 304. By way of example, not limitation, the storage device 302 is a flash memory device, such as a NAND flash application. When the storage controller 300 receives a host output A1 from the host 306 via the host interface 304, the hard encoder 320 performs a hard encoding operation upon input data A1″ to generate encoded data A1′, where the input data A1″ are generated from the host output A1. For example, the input data A1″ are generated from the host output A1 without any change made to the host output A1. In other words, the input data A1″ and the host output A1 are exactly the same. In addition, the hard encoder 320 may be an RS encoder or a BCH encoder. However, this is for illustrative purposes only. That is, any coding scheme which produces encoded data inapplicable to a soft decoding operation with acceptable computational complexity may be employed by the hard encoder 320 in the exemplary storage controller 300. The control circuit 330 is coupled to the hard encoder 320 and the soft encoder 310, and is configured to generate input data A2 for the soft encoder 310 according to the encoded data A1′. In one implementation, the input data A2 are generated from the encoded data A1′ without any change made to the encoded data A1′. In other words, the input data A2 and the encoded data A1′ are exactly the same. However, in an alternative design, the control circuit 330 may apply particular signal processing to the encoded data A1′ prior to generating the input data A2 for the soft encoder 310. This also falls within the scope of the present invention.

The soft encoder 310 performs a soft encoding operation upon the input data A2 to generate encoded data A2′. For example, the soft encoder 310 may be an LDPC encoder, a BTC encoder or a CTC encoder. Specifically, the coding scheme which is capable of producing encoded data applicable to a soft decoding operation with acceptable computational complexity can be employed by the soft encoder 310 in the exemplary storage controller 300. The control circuit 330 is coupled to the soft encoder 310 and the storage device 302, and is configured to record data into the storage device 302 according to the encoded data A2′ generated from the soft encoder 310. In one implementation, the control circuit 330 may directly store the encoded data A2′ into the storage device 302 to accomplish the write operation. In another implementation, the control circuit 330 further processes the encoded data A2′, and then stored a processing result of the encoded data A2′ into the storage device 302 to accomplish the write operation. For example, the control circuit 330 performs a bit interleaving operation upon the encoded data A2′, and then stores a bit-interleaved result of the encoded data A2′ into the storage device 302.

With regard to the read operation, the control circuit 330 reads data from the storage device 302 to obtain readout data B1. For example, in a case where the control circuit 330 directly stores the encoded data A2′ generated from the soft encoder 310 into the storage device 302 to accomplish the write operation, the data read from the storage device 302 are representative of the encoded data A2′. Therefore, the control circuit 330 directly obtains the readout data B1 from the data read from the storage device 302. However, in another case where the control circuit 330 applies specific signal processing upon the encoded data A2′ prior to storing the encoded data A2′ into the storage device 302 (e.g., the control circuit 330 performs a bit interleaving operation upon the encoded data A2′, and then stores a bit-interleaved result of the encoded data A2′ into the storage device 302), the data read from the storage device 302 are representative of a specific signal processing result of the encoded data A2′ rather than the encoded data A2′. Therefore, the control circuit 330 applies an inverse signal processing operation (e.g., a bit deinterleaving operation) upon the data read from the storage device 302 to generate a corresponding signal processing result (e.g., a bit-deinterleaved result), and then obtains the readout data B1 from the corresponding signal processing result. The soft decoder 340 is used for performing a soft decoding operation upon the readout data B1 to generate decoded data B1′. For example, when the soft encoder 310 is an LDPC encoder, the readout data B1 include LDPC codewords, and the soft decoder 340 is an LDPC decoder which decodes the LDPC codewords of the readout data B1 to derive the decoded data B1′; when the soft encoder 310 is a BTC encoder, the readout data B1 include BTC codewords, and the soft decoder 340 is a BTC decoder which decodes the BTC codewords of the readout data B1 to derive the decoded data B1′; and when the soft encoder 310 is a CTC encoder, the readout data B1 include CTC codewords, and the soft decoder 340 is a CTC decoder which decodes the CTC codewords of the readout data B1 to derive the decoded data B1′.

Next, the control circuit 330 generates input data B2 for the hard decoder 350 according to the decoded data B1′. In one implementation, the input data B2 are generated from the decoded data B1′ without any change made to the decoded data B1′. In other words, the input data B2 and the decoded data B1′ are exactly the same. However, in an alternative design, the control circuit 330 may apply particular signal processing to the decoded data B1′ prior to generating the input data B2 to the hard encoder 350. This also falls within the scope of the present invention.

The hard decoder 350 is used for performing a hard decoding operation upon the input data B2 to generate decoded data B2′. For example, when the hard encoder 320 is an RS encoder, the input data B2 include RS codewords, and the hard decoder 350 is an RS decoder which decodes the RS codewords of the input data B2 to generate the decoded data B2′; and when the hard encoder 320 is a BCH encoder, the input data B2 include BCH codewords, and the hard decoder 350 is a BCH decoder which decodes the BCH codewords of the input data B2 to generate the decoded data B2′. In the end, the control circuit 330 transmits a host input B2″ to the host 306 via the host interface 304 to accomplish the read operation, where the host input B2″ is generated from the decoded data B2′. For example, the host input B2″ is generated from the decoded data B2′ without any change made to the decoded data B2′. In other words, the host input B2″ and the decoded data B2′ are exactly the same.

It should be noted that when the storage device 302 is read, the data signal transmitted from the storage device 302 to the control circuit 330 carries soft information read from the storage device 302, where the data signal may be an analog signal (e.g., an analog voltage signal) or a multi-level (multi-bit) signal. In a case where the data signal is an analog voltage signal which transfers an analog voltage derived from reading a data bit stored in each memory cell of the storage device 302, the control circuit 330 has an analog-to-digital conversion capability to convert the analog voltage signal in an analog domain into digital soft bits in a digital domain, and then obtains the readout data B1 according to the digital soft information. As the present invention does not focus on the generation and transmission of the soft bit information, further description is omitted here for the sake of brevity.

In view of above, an exemplary storage control method employed by the storage controller 300 shown in FIG. 3 for controlling data write of a storage device includes following steps: performing a hard encoding operation upon input data to generate encoded data, where the computational complexity of decoding the encoded data via soft decoding is beyond a predetermined acceptable range; performing a soft encoding operation upon another input data, which are derived from the encoded data generated from the hard encoding operation, to generate another encoded data, where the computational complexity of decoding the another encoded data via soft decoding is within the predetermined acceptable range; and recording data into the storage device according to the another encoded data; additionally, the exemplary storage control method employed by the storage controller 300 shown in FIG. 3 for controlling data read of the storage device includes following steps: reading data from the storage device to obtain readout data, performing a soft decoding operation upon the readout data to generate an decoded data, and performing a hard decoding operation upon another input data, which are derived from the decoded data generated from the soft decoding operation, to generate another decoded data. In one exemplary implementation, the input data to be encoded by the soft encoding operation and the encoded data generated from the hard encoding operation are exactly the same, and the input data to be decoded by the hard decoding operation and the decoded data generated from the soft decoding operation are exactly the same. As a person skilled in the art can readily understand details of the exemplary storage control method after reading above paragraphs directed to the storage controller 300, further description is omitted here for brevity.

FIG. 4 is a block diagram illustrating an exemplary system 400 having a storage controller 401 included therein. The exemplary system 400 includes the storage controller 401, a storage device (e.g., a NAND flash) 402, a host interface 404, and a host 406. The storage controller 401 is used for controlling data access of the storage device 402, and communicates with the host 406 via the host interface 404. The storage controller 401 includes, but is not limited to, a soft encoder (e.g., an LDPC encoder for generating LDPC codes or turbo encoder for generating BTC/CTC codes) 410, a hard encoder (e.g., a BCH encoder for generating BCH codes or RS encoder for generating RS codes) 420, a control circuit 430, a soft decoder (e.g., an LDPC decoder for decoding LDPC codes or turbo decoder for decoding BTC/CTC codes) 440, a hard decoder (e.g., a BCH decoder for decoding BCH codes or RS decoder for decoding RS codes) 450, and a data buffer 460 for buffering data processed/generated in the storage controller 401. As can be seen from FIG. 3, the controller architecture of the storage controller 401 shown in FIG. 4 is based on that of the storage controller 300. As a person skilled in the art can readily understand details of the storage controller 401 after reading above paragraphs directed to the storage controller 300, further description is omitted for brevity.

It should be noted that the soft information derived from the storage device 402 may be an analog signal (e.g., an analog voltage signal) or a multi-level signal. For example, if the storage device 402 is equipped with analog-to-digital conversion (A/D) capability, the soft information generated from the storage device 402 is carried by the multi-level signal generated from an analog-to-digital converter (ADC) 470 implemented in the storage device 402. However, if the ADC 470 is implemented in the control circuit 430 rather than the storage device 402, the soft information generated from the storage device 402 is carried by the analog signal, where the ADC 470 in the control circuit 430 will convert the analog signal into a corresponding digital signal.

In a case where the soft encoder 410 is an LDPC encoder, the hard encoder 420 is a BCH encoder, the soft decoder 440 is an LDPC decoder, the hard decoder 450 is a BCH decoder, and the control circuit 430 is also configured for performing bit interleaving, bit deinterleaving and analog-to-digital conversion, the control and data flow of the system 400 is shown in FIG. 5. However, this is for illustrative purposes only, and is not meant to be taken as a limitation to the scope of the present invention.

The aforementioned storage device 102, 302 or 402 may be a NAND flash-based device, such as a solid state drive (SSD). Taking the SSD for example, it is a closed-loop system, therefore the employed encoding and decoding formats thereof can be arbitrarily defined by the storage controller of the SSD as long as the minimum ECC requirement of the NAND flash is satisfied. To meet the high bandwidth requirement of the host, a multi-channel architecture is employed by the NAND flash of the SSD to use a plurality of physical channels for data transmission. Moreover, due to the multi-field characteristic of the SSD, only one filed is allowed to be adjusted, which is different from a nibble-based or byte-based device, such as an optical disc drive (ODD).

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. 

1. A storage controller for controlling data access of a storage device, comprising: a control circuit, configured for reading data from the storage device to obtain readout data; and a soft decoder, coupled to the control circuit, for performing a soft decoding operation upon the readout data to generate first decoded data.
 2. The storage controller of claim 1, further comprising: a hard decoder, coupled to the control circuit, for performing a hard decoding operation upon input data to generate second decoded data; wherein the input data are generated from the control circuit according to the first decoded data.
 3. The storage controller of claim 2, wherein the input data are generated from the first decoded data without any change made to the first decoded data.
 4. The storage controller of claim 2, further comprising: a soft encoder, coupled to the control circuit, for performing a soft encoding operation upon first input data to generate first encoded data; and a hard encoder, coupled to the control circuit, for performing a hard encoding operation upon second input data to generate second encoded data; wherein the control circuit further generates the first input data for the soft encoder according to the second encoded data, and records data into the storage device according to the first encoded data.
 5. The storage controller of claim 4, wherein the first input data are generated from the second encoded data without any change made to the second encoded data.
 6. The storage controller of claim 1, further comprising: a soft encoder, coupled to the control circuit and configured for performing a soft encoding operation upon input data to generate encoded data; wherein the control circuit further records data into the storage device according to the encoded data.
 7. The storage controller of claim 1, wherein the storage device is a flash memory device.
 8. The storage controller of claim 1, wherein the soft decoder is a low density parity check (LDPC) decoder, a block turbo code (BTC) decoder, or a convolutional turbo code (CTC) decoder.
 9. A storage control method for controlling data access of a storage device, comprising: reading data from the storage device to obtain readout data; and performing a soft decoding operation upon the readout data to generate first decoded data.
 10. The storage control method of claim 9, further comprising: performing a hard decoding operation upon input data to generate second decoded data; wherein the input data are generated from the first decoded data.
 11. The storage control method of claim 10, wherein the input data are generated from the first decoded data without any change made to the first decoded data.
 12. The storage control method of claim 10, further comprising: performing a soft encoding operation upon first input data to generate first encoded data; performing a hard encoding operation upon second input data to generate second encoded data, wherein the first input data are generated from the second encoded data; and recording data into the storage device according to the first encoded data.
 13. The storage control method of claim 12, wherein the first input data are generated from the second encoded data without any change made to the second encoded data.
 14. The storage control method of claim 9, further comprising: performing a soft encoding operation upon input data to generate encoded data; and recording data into the storage device according to the encoded data.
 15. The storage control method of claim 9, wherein the storage device is a flash memory device.
 16. The storage control method of claim 9, wherein the soft decoding operation is a low density parity check (LDPC) decoding operation, a block turbo code (BTC) decoding operation, or a convolutional turbo code (CTC) decoding operation.
 17. A system comprising: a storage device; and a storage controller, coupled to the storage device, for controlling data access of the storage device, wherein a data signal transmitted from the storage device to the storage controller carries soft information derived from the storage device.
 18. The system of claim 17, wherein the storage device includes an analog-to-digital converter utilized for generating a multi-level signal as the data signal.
 19. The system of claim 17, wherein the data signal is an analog signal, and the storage controller includes an analog-to-digital converter utilized for converting the analog signal into a corresponding digital signal.
 20. The system of claim 17, wherein the storage device is a flash memory device. 